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Cadence and TSMC Expand Certified AI and HPC Flows Across Advanced Nodes, Chiplets ...

Published

29 September 2026

Topic

technology

◆ Sectors

SemiconductorsAI Infrastructure

◆ Geography

TaiwanUnited States

◆ Source

Read at eetasia.com →

◆ Verified

Fusion42 · 29 September 2026 · Fusion42 review

Cadence and TSMC have expanded certified AI and HPC chip design flows across advanced semiconductor nodes including N3, N2, A16, and A14, supporting chiplets and 3D-IC technologies. This collaboration delivers silicon-proven IP and advanced design tools covering digital, signoff, and custom analog flows, aiming to accelerate tape-outs and enhance power, performance, and area for AI and HPC chips.

This Wire brief sits within Fusion42's coverage of Semiconductors and AI Infrastructure.

◆ ◆ The Wire takeaway

Your AI or HPC chip design now gains faster tape-out paths and proven IP across TSMC's latest nodes, including 3D integration and chiplets, cutting design cycles and boosting competitiveness. Build your chip development roadmap around these certified flows to win in advanced process node projects.

◆ Coverage

1 source · 29 Sep 2026

◆ Related on Wire

◆ Topics

SemiconductorsAI Infrastructurecadencetsmcai-chiphpcchiplets3d-ic